This invention relates to a TTL compatible CMOS input buffer. The invention is useful in achieving input threshold control and matching TTL threshold levels to CMOS levels.
U.S. Pat. No. 4,295,065 to Hsieh et al. discloses a TTL to CMOS input buffer, or level shift circuit, which incorporates a level shift portion comprising CMOS transistors P.sub.1, N.sub.1, P.sub.3, and N.sub.3. These devices are connected in such a manner as to reduce static power consumption by eliminating current paths between nodes 13 and 19 of, for example, the circuits shown in FIGS. 1 and 3b of 4,295,065. With further reference to these same Figures, transistors P.sub.1 and N.sub.1 form an inverter with transistor N.sub.3 connected in series between P.sub.1 and N.sub.1 on the output side. When V.sub.IN is high, P.sub.1 is OFF and N.sub.1 and N.sub.3 are ON, clamping node 15 and terminal 17 to ground. At the same time, P.sub.3 is ON, clamping node 11 to V.sub.DD. When V.sub.IN is low, P.sub.1 is ON clamping node 15 to V.sub.DD, P.sub.3 is OFF due to the V.sub.DD potential at node 15, and N.sub.1 and N.sub.3 are OFF. Thus, terminal 17 is allowed to float and is isolated from both terminal 15 (V.sub.DD) and terminal 19 (ground).
Since N.sub.1 and N.sub.3 act as a voltage divider when V.sub.IN is high, the channel resistance, R.sub.ON, of N.sub.3 is an important parameter in the design of this circuit. The equation for channel resistance of a CMOS device is R.sub.ON =channel length/(channel width.times.k'.times.2 (V.sub.GS -V.sub.t)). Thus, for devices of the same length, R.sub.ON is affected by variations in channel width and V.sub.GS. The remaining variables (k' and V.sub.T) in the equation have equal effects on all devices located on a common chip, as is the case in circuits of the type illustrated in U.S. Pat. No. 4,295,065 and in the present application. This means that, for the circuit shown in 4,295,065, a certain channel width must be provided in order to maintain R.sub.ON at acceptable levels. This requirement has a disadvantageous impact upon the density of devices on a given chip.
Another disadvantage of circuits of the type illustrated in U.S. Pat. No. 4,295,065 is that when V.sub.IN (refer to FIG. 2 of the present application) is low (for example, 0.8 V) and the gate of N.sub.3 is connected to V.sub.IN, the output of the inverter circuit can have an additional state. This is due to the fact that, as noted above, N.sub.3 in this circuit is off or highly resistive when V.sub.IN is low. In order to keep the inverter formed by P.sub.1 and N.sub.1 from "tristating," an additional voltage source (V.sub.C) and two additional devices (P.sub.2 and N.sub.2) are required.
An object of the present invention is to provide a TTL to CMOS input buffer circuit which allows device width to be decreased while channel resistance is held constant, permitting increased device density on a chip.
Another object of the present invention is to provide a TTL to CMOS input buffer circuit which can be implemented with a minimal number of devices, which requires a minimal number of voltage sources, and which consumes a minimal amount of power.
In the circuit of the present invention, a transistor is provided which has a gate terminal connected directly to the power supply terminal V.sub.DD. This connection allows for a decrease in device width, while a constant channel resitance R.sub.ON is maintained. This decrease in device width allows for greater device density on a given chip.
The circuit of the present invention also eliminates the tristating problem discussed above. The additional components (P.sub.2 and N.sub.2) and power supply (V.sub.C) required in prior art circuits are eliminated. Thus, the circuit can be implemented with a minimal number of components and consumes a minimal amount of power.
The circuit of the present invention comprises: a first field effect transistor of one conductivity type and a second field effect transistor of the other conductivity type, each of said first and second transistors having a main current conducting path; a third field effect transistor also having a main current conducting path; means for coupling the main current conducting path of the third transistor in series between the main current conducting paths of the first and second transistors, each of the first, second and third transistors having a control electrode, the signal level on which controls current flow through the main current conducting path thereof; means for coupling the control electrodes of the first and second transistors to the output of a TTL circuit, the output signal of which is to be converted to a CMOS logic level; means for coupling the main current conducting path of the third transistor to the buffer output; and means for coupling the control electrode of the third transistor to a voltage source having an absolute magnitude which is greater than the voltage on the control electrodes of the first and second transistors (i.e. V.sub.in from the TTL circuit). This source of voltage is, in the preferred embodiment discussed below, the CMOS voltage source V.sub.DD. However, the TTL voltage source, V.sub.CC, or an independent voltage source could also be used. It should also be noted that a single voltage source can be used for both V.sub.CC and V.sub.DD. However, this is not a necessity and, in the embodiment discussed below, V.sub.DD is unrelated to the voltage source V.sub.CC of the TTL circuit, the output of which the invention buffers. In a preferred embodiment, the second and third transistors are of the same conductivity types.
Another embodiment of the circuit of the present invention further comprises a fourth transistor having a main current conducting path and a control electrode, means for coupling the main current conducting path of the fourth transistor between the terminal of the CMOS voltage supply to which the main current conducting path of the first transistor is coupled and the output terminal, and means for coupling the control electrode of the fourth transistor to the output of the TTL circuit.
In yet another preferred embodiment of the circuit of the present invention, the means for coupling the main current conducting path of the third transistor to the buffer output comprises a fifth bipolar transistor having a main current conducting path and a control electrode, means for coupling the control electrode of the fifth transistor to the source of the third transistor, and means for coupling the main current conducting path of the fifth transistor between the output of the level conversion circuit and the voltage source having an absolute magnitude which is greater than the voltage on the control electrodes of the first and second transistors. The bipolar transistor employed may be a common parasitic device produced in conjunction with the CMOS circuits. The bipolar device provides a degree of temperature compensation to the output of the circuit, due to variations in V.sub.BE of the device, as will be described in detail below.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.